VotaryTech Celebrates its 9th ANNIVERSARY
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Any product/system development typically involves both hardware and software designing that generally proceeds in parallel. Hardware designs these days are mostly in the form of SoC’s that consist of one or more microcontroller/microprocessor cores to run the software along-with remaining system hardware logic.

Design Implementation

VotaryTech has domain expertise to enable you to develop solutions for a vast array of industry sectors. We are well-versed on the latest interface protocols and embedded CPU/GPU processor and memory subsystem design techniques. Our engineers are trained on the latest developments in the areas of high performance, low power and area efficient designs. We have delivered many FGPA prototypes and also conversions of FPGA to ASIC.

Design Verification

VotaryTech has built the verification expertise around the latest methodologies, in particular System Verilog with OVM/UVM. Our teams have been involved in the development of advanced verification methodologies for many tier-1 semiconductor companies, utilizing not only OVM/UVM, but also techniques such as constrained random generation, functional coverage and assertion-based verification.

With our emphasis on both digital and mixed signal designs, VotaryTech has considerable experience with mixed mode simulation methodologies.
We have expertise with simulators, debugging tools, formal verifiers and hardware accelerators from all the major EDA tool suppliers.

Physical Design

VotaryTech delivered production tapeouts using Synopsys, Cadence & Mentor tools. We have experience on the very latest process technology nodes, down to 28nm, 14nm, 10nm.

Our tool flows are captured using a proprietary technology that enables a repeatable, rules-driven solution, which in turn drives our industry-leading first time silicon success rate.

ASIC Design & FPGA Design

The hardware design on a broader scale can be divided into two categories: ASIC (Application Specific Integrated Circuit) design and FPGA (Field Programmable Gate Array) based design. ASIC design is more complex and time consuming but cost effective and customizable for volume production. On the other hand, FPGA design is simpler and faster but costly when applied to volumes and hence meant for specific usage.

Typical ASIC design flow with ordered steps:

Design Spec → RTL (Register Transfer Level) coding → Functional/Gate level verification → Synthesis → Design for testability (DFT) → Place and route (P&R) → Static Timing Analysis (STA) → Timing Extraction → GDSII

Typical FPGA design flow with ordered steps:

Design Spec → RTL coding → Functional/Gate level verification → Synthesis → Place and route (P&R) → Static Timing Analysis (STA) → Download on FPGA

At Votary tech, with our talented and experienced team, we provide quality design and verification services to achieve faster time to market. With our software and Hardware skills put together we can provide a complete embedded system.

VotaryTech has extensive resources to provide design verification and validation services spanning analog, mixed-signal, ASIC, SoC, digital logic and custom IP. The validation process includes pre-silicon, post-silicon and system validation.

We apply advanced verification methodologies for projects by aligning them to the client’s process including the use of high-level verification languages like SystemVerilog UVM (universal verification methodology), Verilog-AMS and more.

The modern digital logic verification involves constrained random testing, functional coverage, and assertion-based verification. Our emphasis on both digital and mixed-signal designs enables us to provide experienced engineering resources in mixed-mode simulation methodologies. We also have dedicated engineers experienced with Verilog-AMS (analog-mixed-signal) who create mixed-signal verification environments for advanced mixed-signal ICs. And we have delivered the latest verification environments using the Verilog-A/AMS and RNM Real Number Modeling) for our clients.

Implementation of 4K up scaling on ZCU102

AXI4 bus functional model and Functional simulation of the RTL.