Design Verification

VotaryTech has built the verification expertise around the latest methodologies, in particular System Verilog with OVM/UVM. Our teams have been involved in the development of advanced verification methodologies for many tier-1 semiconductor companies, utilizing not only OVM/UVM, but also techniques such as constrained random generation, functional coverage and assertion-based verification.

With our emphasis on both digital and mixed signal designs, VotaryTech has considerable experience with mixed mode simulation methodologies.
We have expertise with simulators, debugging tools, formal verifiers and hardware accelerators from all the major EDA tool suppliers.

Design Verification2