The hardware design on a broader scale can be divided into two categories: ASIC (Application Specific Integrated Circuit) design and FPGA (Field Programmable Gate Array) based design. ASIC design is more complex and time consuming but cost effective and customizable for volume production. On the other hand, FPGA design is simpler and faster but costly when applied to volumes and hence meant for specific usage.
Typical ASIC design flow with ordered steps:
Design Spec → RTL (Register Transfer Level) coding → Functional/Gate level verification → Synthesis → Design for testability (DFT) → Place and route (P&R) → Static Timing Analysis (STA) → Timing Extraction → GDSII
Typical FPGA design flow with ordered steps:
Design Spec → RTL coding → Functional/Gate level verification → Synthesis → Place and route (P&R) → Static Timing Analysis (STA) → Download on FPGA
At Votary tech, with our talented and experienced team, we provide quality design and verification services to achieve faster time to market. With our software and Hardware skills put together we can provide a complete embedded system.
VotaryTech has extensive resources to provide design verification and validation services spanning analog, mixed-signal, ASIC, SoC, digital logic and custom IP. The validation process includes pre-silicon, post-silicon and system validation.
We apply advanced verification methodologies for projects by aligning them to the client’s process including the use of high-level verification languages like SystemVerilog UVM (universal verification methodology), Verilog-AMS and more.
The modern digital logic verification involves constrained random testing, functional coverage, and assertion-based verification. Our emphasis on both digital and mixed-signal designs enables us to provide experienced engineering resources in mixed-mode simulation methodologies. We also have dedicated engineers experienced with Verilog-AMS (analog-mixed-signal) who create mixed-signal verification environments for advanced mixed-signal ICs. And we have delivered the latest verification environments using the Verilog-A/AMS and RNM Real Number Modeling) for our clients.
FPGA based H/W development project end –end prototyping and silicon validation
Multimedia 4k & 8K upscaling project
• Implementation of 4K & 8K upscaling multimedia project on MPSOC based hardware.
• By interfacing 3A camera (IMX274) which has the MIPICSITX interface
• Where MIPICSIRX IP core which is integrated in the PL section of SOC
• The IP cores used in PL section are MIPICSIRX ,HDMITX,Demosaic,GammaLUT, 3D filters, image upscaling, image down scaling algorithms written in Verilog.
• Boardsupport packages, baremetal application were written in C, Developed yocto images using Linux for the complete target hardware
SOFTWARE DEFINED RADIO ON INTEL HARDWARE
Votarytech SDR platform is a Generic platform supports in both Transmitting and receiving the RF frequencies, where this platform supports all the signal processing modulation and demodulation Techniques were implemented in the Aria 10AX115U3F4512SG, due to the programmability of the Aria SOC it is very convenient to implement and fine tune the base band processing modules like Digital up conversion, digital down conversion, Modulator ip cores and demodulator ip cores can be configured and Reprogrammable very easily, Implementation of software defined radio on the INTEL aria 10AX115U3F45I2SG custom hardware board, where it has a 4 channel, 12 bit, 10 GSPS Analog-to-Digital converter , it has the mixer , LNA,power amplifier which is interfaced to the Diplexer antenna, where it acts like a Transceiver,it transmits 2 GHZ of signal and captures the digital baseband output, complete Base band application is implemented inside the FPGA, which is written in Verilog software both BPSK modulator , demodulator IP cores were developed inside the FPGA, This product is capable of programming both hardware and software, it can be tunable in transmitting the frequencies from 50MHZ to 2.5GHZ sampling frequencies, It can be used as the programmable Software defined radio, and as well as the wave form generation,
Intel Arria 10 FPGAs deliver more than a speed grade faster core performance and up to a 20% fMAX advantage for publicly available OpenCore designs. 20nm design lower power dissipation
• 1,150k Logic Elements (LEs)
• 53 Mb M20K memory
• 3,036 18 x 19-bit multipliers
• 1,518/1,518 hardened single-precision floating-point multipliers/adders
• Ease of accessing the circuit schematics and availability of the gerber and board files for the eval platforms made more convenient to develop the hardware.
Diplexer Base band processing implemented on Intel Aria
The Base band processing consists of the Digital up conversion and digital Down conversion, Communication standard Modulator and demodulator cores which were written in Verilog codes which are developed performed Simulation and Synthesizable IP cores were used and integrated inside the FPGA section, ADC output and DAC input is given to the base band section inside the FPGA.